1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a surrounding gate transistor (SGT) and a production method therefor.
2. Description of the Related Art
A miniaturized planar transistor is used in a wide range of fields, such as computers, communication apparatuses, measurement instruments, automatic control units and domestic appliances, as a fundamental element of low-power consumption, low-cost and high-throughput microprocessors, ASICs and microcomputers and low-cost and large-capacity memories. However, the planar transistor is formed on a semiconductor substrate in a planar configuration, i.e., in a configuration where a source, a gate and drain are horizontally arranged along a surface of a silicon substrate. In contrast, an SGT has a structure where a source, a gate and a drain are arranged in a direction perpendicular to a silicon substrate, and wherein the gate is disposed to surround a convex-shaped semiconductor layer (see, for example, the following Non-Patent Document 1; FIG. 113). Thus, as compared with the planar transistor, the SGT is capable of significantly reducing a transistor occupancy area. However, in a conventional SGT structure, along with the progress in reducing the scale of the SGT structure, an area ratio of a gate electrode to a total transistor occupancy area becomes larger. In addition, due to reducing the scale of a silicon pillar, a resistance in each of source and drain regions formed in the silicon pillar is increased, and thereby an ON current is reduced.
For this reason, a buried-gate SGT (BG-SGT) has been proposed which has an SGT structure where a gate is buried in a silicon pillar (see, for example, the following Non-Patent Document 2; FIG. 114). In this structure, a silicon pillar can be formed to have a small-diameter channel region and large-diameter source and drain regions, so as to simultaneously meet a need for suppressing short-channel effects and a need for reducing a resistance in each of the source and drain regions, i.e., achieve a reduction in OFF-current and an increase in ON-current.
However, as regards to a need for ensuring a low parasitic capacitance to achieve an increase in speed and power consumption reduction in an LSI circuit, the conventional BG-SGT is incapable of achieving such a low parasitic capacitance between the gate and the source or between the gate and the drain.
In this connection, as a technique for reducing a gate-drain parasitic capacitance and a gate-source parasitic capacitance to achieve an increase in speed of the circuit, a vertical replacement gate (VRG)-MOSFET has been known (see, for example, the following Non-Patent Document 3 and Patent Document 1; FIG. 115) and other techniques (see, for example, the following Patent Document 2; FIG. 116).
FIG. 115 shows the VRG-MOSFET (the Patent Document 1). A gate adjacent a silicon pillar faces not only a silicon pillar through a gate oxide layer but also each of a source region and a drain region through an interlayer insulating film. Thus, in addition to a gate capacitance between the gate and the silicon pillar, parasitic capacitances are produced between the gate and the source and between the gate and the drain, respectively. A structure proposed here is intended to increase a film thickness of the interlayer insulating film between the gate and the source to increase a distance therebetween and increase a film thickness of the interlayer insulating film between the gate and the drain to increase a distance therebetween, so as to reduce the respective parasitic capacitances.
FIG. 116 shows an SGT having a structure intended to reduce a parasitic capacitance between a gate and a source, as disclosed in the Patent Document 2. A gate adjacent a silicon pillar faces not only a silicon pillar through a gate oxide layer but also a source region through an interlayer insulating film. Thus, in addition to a gate capacitance between the gate and the silicon pillar, a parasitic capacitance is produced between the gate and the source. A structure proposed here is intended to increase a film thickness of the interlayer insulating film between the gate and the source to increase a distance between the gate and the source, so as to reduce the parasitic capacitance.    Non-Patent Document 1: H. Takato et al, IEEE transaction on electron devices, Vol. 38, No. 3, March 1991, p 573-578    Non-Patent Document 2: M. Iwai et al, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, 2003, p 630-631    Non-Patent Document 3: IEDM 1999 John M. Hergenrother    Patent Document 1: U.S. Pat. No. 6,027,975 (Feb. 22, 2000, John M. Hergenrother)    Patent Document 2: U.S. Pat. No. 5,504,359 (Apr. 2, 1996, Mark S. Rodder)